1. Field of the Invention
The present invention relates to a multilayer chip capacitor, more particularly, which can be reduced in size and equivalent series inductance (ESL).
2. Description of the Related Art
In general, a multilayer chip capacitor has internal electrodes of different polarities deposited alternately to interpose each of dielectric layers. This multilayer chip capacitor advantageously ensures a smaller size, a higher capacity and easy mountability on a circuit board, thus widely used as a capacitive component of various electronic devices. Especially, the multilayer chip capacitor is considerably utilized as a decoupling capacitor for stabilizing a high frequency power circuit for use in e.g., a micro-processor unit (MPU). To be employed as a decoupling capacitor of the MPU, the capacitor should have a low ESL. This demand for a lower ESL has been rising due to a higher speed of the MPU and a resultant higher power and lower voltage trend.
To be employed in an MPU package, decoupling capacitors need to be connected in parallel to lower impedance of a power network. Here, a greater number of the decoupling capacitors with a smaller size should be connected in parallel to achieve lower impedance due to a limited mounting area. Even though the decoupling capacitors are smaller-sized, that is, a greater number of capacitors are connected in parallel in a limited mounting area, the smaller-sized capacitors may achieve less decline in overall impedance when each of the capacitors is increased in an ESL. Therefore, to reduce size of the decoupling capacitors, it is of great importance to keep an ESL of the each capacitor at an identical or lower level compared to a non-downscaled capacitor.
FIG. 1A is a schematic perspective view illustrating a conventional multilayer chip capacitor and FIG. 1B is a side cross-sectional view illustrating the conventional multilayer chip capacitor.
Referring to FIGS. 1A and 1B, the multilayer chip capacitor 10 includes a capacitor body 11 having a plurality of dielectric layers deposited therein. First or second internal electrodes 12 and 13 are formed on each of the dielectric layers. The first and second internal electrodes 12 and 13 are disposed to oppose each other while interposing the each dielectric layer. Thus, the first and second internal electrodes 12 and 13 are connected to first and second external electrodes 14 and 15 of different polarities formed on end faces of the capacitor body 11. Generally, each the external electrodes 14 and 15 has an extending portion A partially extended to a top and bottom and sides adjacent to the end faces.
This multilayer chip capacitor 10, as illustrated in an equivalent circuit diagram of FIG. 1C, has an equivalent series inductance (ESL) resulting from current loop in the capacitor and an equivalent series resistance (ESR) resulting from dielectric loss and electrode resistance, in addition to its intended capacitance C. This two-terminal capacitor is too high in an ESL to be used as a high-performing decoupling capacitor for a high frequency circuit.
Recently, a multi-terminal multilayer chip capacitor such as an eight-terminal capacitor has been suggested as a decoupling capacitor. For example, U.S. Pat. No. 5,880,925 assigned to AVX Corporation discloses an eight-terminal multilayer chip capacitor in which leads of internal electrodes of different polarities are arranged interdigitatedly, and also a plus (+) external terminal and a minus (−) external terminal are arranged alternately to cancel out magnetic fluxes generated by high frequency currents, thereby decreasing the ESL. In general, a greater number of electrodes (terminals) further reduce the ESL, but during a current process of forming the external electrodes, four terminals are arranged on one side (longer side) of the capacitor body. The eight-terminal capacitor with a 1680 size, which adopts the AVX structure, has an ESL of approximately 60 pH.
As described above, to lower overall impedance, a greater number of smaller multi-terminal capacitors should be connected in parallel in a limited mounting area. In a case where the AVX-suggested capacitor structure is reduced from a 1608 size (a length of 1.6 mm and a width of 0.8 mm) to a 1005 size (a length of 11.0 mm and a width of 0.5 mm), only three terminals may be arranged on one longer side face due to limitation associated with the formation process of the external electrodes. Therefore, the capacitor structure, when reduced from a 1608 size to a 1005 size, is expected to adopt a six-terminal capacitor. Here, the six-terminal capacitor with a 1005 size has a smaller number of terminals than an eight-terminal capacitor with a 1608 size, and thus is increased in an ESL to approximately 75 pH. Accordingly, the plurality of capacitors connected in parallel lead to less decrease in total inductance. In consequence, such reduction in size of the capacitor requires a smaller number of external terminals, which however subsequently increases the ESL of each of the capacitors.